18FxxQ43 SRAM silicon errata B0

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Jerry Messina
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18FxxQ43 SRAM silicon errata B0

Post by Jerry Messina » Sat Jun 27, 2020 11:06 am

Just a heads up to anyone looking at using the Q43...
There's a nasty silicon errata just published that basically makes the chips unusable!

18FxxQ43 errata issue 1.4.1
silicon rev B0

SRAM Readback
-------------
Following a device power up sequence, there is a possibility that some SRAM locations will not return the expected
written value but will read back '00' instead.

Work around:
None. The device can only recover by power cycling.

This erroneous condition can be detected by running the following code that writes non-zero values to SRAM and
then verifies the returned read values are not '00'. If a returned value is '00', the application code should be put
into a safe state until a POR event occurs. This code should be executed immediately after power-up.
If the test passes, device operation will be normal.

Code: Select all

// SRAM test
// For devices up to 2K RAM
FSR0 = $0cff  // Write data into RAM
INDF0 = $55
PROD = INDF0  // Read back data
if (PROD = 0) then
    SAFE_STATE()  // RAM incorrectly read, suspend operation and go to safe state
endif

// For devices with more than 2K of SRAM add the following code
FSR0 = $14ff  // Write data into RAM
INDF0 = $55
PROD = INDF0  // Read back data
if (PROD = 0) then
    SAFE_STATE()  // RAM incorrectly read, suspend operation and go to safe state
endif

// For devices with more than 4K of SRAM add the following code
FSR0 = $24ff  // Write data into RAM
INDF0 = $55
PROD = INDF0  // Read back data
if (PROD = 0) then
    SAFE_STATE()  // RAM incorrectly read, suspend operation and go to safe state
endif

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David Barker
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Re: 18FxxQ43 SRAM silicon errata B0

Post by David Barker » Sat Jun 27, 2020 12:09 pm

That's unbelievable!!

You have to perform a hard reset (recycle power). Yeah, right.

Pass me the bin...

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Re: 18FxxQ43 SRAM silicon errata B0

Post by bitfogav » Sat Jun 27, 2020 12:47 pm

Probably just a good idea to stay away from that specific chip! :shock:

W4GNS
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Re: 18FxxQ43 SRAM silicon errata B0

Post by W4GNS » Sat Jun 27, 2020 2:22 pm

Thanks for pointing that out Jerry.
Gary W4GNS

Jerry Messina
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Re: 18FxxQ43 SRAM silicon errata B0

Post by Jerry Messina » Sat Jun 27, 2020 3:31 pm

I'm hoping that errata reads "we really screwed up on this one and while we fix it we thought you should know..."

Otherwise they can't be serious, can they?

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Re: 18FxxQ43 SRAM silicon errata B0

Post by W4GNS » Sat Jun 27, 2020 3:39 pm

The sad part is Microchip bought out Atmel, so it's just a matter of time before they screw up the avr's.
A shakeup in upper management at Microchip would be a good move.
Gary W4GNS

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octal
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Re: 18FxxQ43 SRAM silicon errata B0

Post by octal » Sun Jun 28, 2020 8:52 am

Jerry Messina wrote:
Sat Jun 27, 2020 3:31 pm
I'm hoping that errata reads "we really screwed up on this one and while we fix it we thought you should know..."

Otherwise they can't be serious, can they?
This is serious Jerry, this is Microchip since some years. I saw this kind of behaviour and lose of seriousness at Microchip when they released PIC32MZ series. When I saw first errata sheet, I did said to some colleagues that they released a proto, and as I know Microchip is very serious they'll for sure release corrected versions in few months. 6 years latter, they still didn't corrected their silicon, they instead ammended the errata datasheet by adding incredible things like I2C doesn"t work and the workarround is to use bitbanging I2C ...
This greatly explain CortexM0/M3/M4 vendors success and Microchip 32bit fail (despite the fact that their MIPS core is really great).

A pitty ...

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