CONFIG GENERATAOR FOR 18F27Q84

[garryp4]

I am trying to program a 18F27Q84 using an NSDSP-2-X programmer from Northern Software. I know it works fine and all the connections are fine as I can program a different circuit with a 18F14Q41. For years I have used the programmer from MELABS which did not require a Config block inside my code. Inorder to use the NSDSP programmer I need to include the Config block. The Swordfish Config Generator utility created the Config Block for the 18FQ41 just fine. However the Config Block from the generator for the 18F27Q84 does not seem to work. I can load a program with the MELABS programmer the code works fine but when usuing the NSDSP, the program does not work as the LCD on the circuit shows garbage.

So I compared the number of config options from the MELABS Config utility which is 45, and the number of config options from the Config Generator utility which is 37. Then I looked at the data sheet. The data sheet has more config options than the generator does. The first is DEBUG in register CONFIG7 and the rest are in registers CONFIG9 / 10. Are these needed?

Thanks.

[Jerry Messina]

Here's some background on this...

The Q83/Q84 actually have 35 CONFIG registers, located from $300000-$300022
However, there's a problem. In absolute mode, the MPASMX assembler won't let you use the 'CONFIG' directive with >16 config bytes...
past that you get random assembly errors, MPASMX blows up, and generates "unknown error".
There's a detailed description in the SF library file 'Library\config_Q84.bas'

To get around this problem I changed the MPASMX .info file to remove many of the registers, most of which have to do
with CRC generation at PON and integrity checks. The file config_Q84.bas lets you insert data directly into the hex file for
these registers if need be.

You can usually get by with all of the extra CONFIG registers left at the default state ($FF).
If the chip doesn't run, make sure you have

Code: Select all

config JTAGEN = OFF             // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
config MVECEN = OFF             // Interrupt contoller does not use vector table to prioritze interrupts
config XINST = OFF              // Extended Instruction Set and Indexed Addressing Mode disabled

You don't normally need all of them, but to generate data for ALL of the registers, use the ConfigGenerator to get the settings
for the "normal" registers, set the others using the '#variable' definitions outlined in the device file, and include config_Q84.bas.
That should generate a hex file with data for all 35 CONFIG registers... if you don't include config_Q84.bas then you'll get a hex file
with only the first 10 locations set ($300000-$300009)

Here's an example:
NOTE - if you actually enable any of these extended registers you can make it fail the integrity checks and it won't boot!

Code: Select all

device=18F27Q84
clock=64

// from ConfigGen tool 
config FEXTOSC = ECH            // EC (external clock) above 8 MHz
config RSTOSC = EXTOSC          // EXTOSC operating per FEXTOSC bits (device manufacturing default)
config CLKOUTEN = OFF           // CLKOUT function is disabled
config PR1WAY = ON              // PRLOCKED bit can be cleared and set only once
config CSWEN = ON               // Writing to NOSC and NDIV is allowed
config JTAGEN = OFF             // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
config FCMEN = ON               // Fail-Safe Clock Monitor enabled
config FCMENP = ON              // FSCM timer will set FSCMP bit and OSFIF interrupt on Primary XTAL failure
config FCMENS = ON              // FSCM timer will set FSCMS bit and OSFIF interrupt on Secondary XTAL failure
config MCLRE = EXTMCLR          // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
config PWRTS = PWRT_64          // PWRT set at 64ms
config MVECEN = OFF             // Interrupt contoller does not use vector table to prioritze interrupts
config IVT1WAY = ON             // IVTLOCKED bit can be cleared and set only once
config LPBOREN = OFF            // Low-Power BOR disabled
config BOREN = ON               // Brown-out Reset enabled according to SBOREN
config BORV = VBOR_1P9          // Brown-out Reset Voltage (VBOR) set to 1.9V
config ZCD = OFF                // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
config PPS1WAY = ON             // PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
config STVREN = ON              // Stack full/underflow will cause Reset
config LVP = ON                 // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
config XINST = OFF              // Extended Instruction Set and Indexed Addressing Mode disabled
config WDTCPS = WDTCPS_31       // Divider ratio 1:65536; software control of WDTPS
config WDTE = OFF               // WDT Disabled; SWDTEN is ignored
config WDTCWS = WDTCWS_7        // window always open (100%); software control; keyed access not required
config WDTCCS = SC              // Software Control
config BBSIZE = BBSIZE_512      // Boot Block size is 512 words
config BBEN = OFF               // Boot block disabled
config SAFEN = OFF              // SAF disabled
config DEBUG = OFF              // Background Debugger disabled
config WRTB = OFF               // Boot Block not Write protected
config WRTC = OFF               // Configuration registers not Write protected
config WRTD = OFF               // Data EEPROM not Write protected
config WRTSAF = OFF             // SAF not Write Protected
config WRTAPP = OFF             // Application Block not write protected
config BOOTPINSEL = RC5         // CRC on boot output pin is RC5
config BPEN = OFF               // CRC on boot output pin disabled
config ODCON = OFF              // Pin drives both high-going and low-going signals
config CP = OFF                 // PFM and Data EEPROM code protection disabled

// extended CONFIG data (XCONFIG)
#variable CRC_CONFIG = BOOTSCEN and BOOTPOR
#variable BCRCPOLT  = $AB
#variable BCRCPOLU  = $CD
#variable BCRCPOLH  = $EF
#variable BCRCPOLL  = $55

#variable BCRCSEEDT = $01
#variable BCRCSEEDU = $02
#variable BCRCSEEDH = $03
#variable BCRCSEEDL = $04
#variable BCRCEREST = $05
#variable BCRCERESU = $06
#variable BCRCERESH = $07
#variable BCRCERESL = $08
#variable CRCPOLT   = $09
#variable CRCPOLU   = $0a
#variable CRCPOLH   = $0b
#variable CRCPOLL   = $0c
#variable CRCSEEDT  = $0d
#variable CRCSEEDU  = $0e
#variable CRCSEEDH  = $0f
#variable CRCSEEDL  = $10
#variable CRCEREST  = $11
#variable CRCERESU  = $12
#variable CRCERESH  = $13
#variable CRCERESL  = $AA

include "config_Q84.bas"

// you code goes here
main:
while (true)
end while

Let me know if you still have problems. Try a blinking LED first and see if that works.

[garryp4]

Jerry:

Thanks for the info. I have included my code with what I had from the ConfigGenerator commented out and what you sent with two changes. I get an error at the DEBUG line:

Code: Select all

Device = 18F27Q84
Clock  = 64
{          This is what I had from the  ConfigGenerator
Config
  FEXTOSC = OFF,      // Oscillator not enabled
  RSTOSC = HFINTOSC_64MHZ,// HFINTOSC with HFFRQ = 64 MHz and CDIV = 4:1
  CLKOUTEN = OFF,     // CLKOUT function is disabled
  PR1WAY = ON,        // PRLOCKED bit can be cleared and set only once
  CSWEN = OFF,        // The NOSC and NDIV bits cannot be changed by user software
  JTAGEN = OFF,       // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
  FCMEN = ON,         // Fail-Safe Clock Monitor disabled
  FCMENP = ON,        // FSCM timer will not set FSCMP bit or OSFIF interrupt on Primary XTAL failure
  FCMENS = ON,        // FSCM timer will not set FSCMS bit or OSFIF interrupt on Secondary XTAL failure
  MCLRE = EXTMCLR,    // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR 
  PWRTS = PWRT_16,    // PWRT is 16 ms
  MVECEN = OFF,       // Interrupt contoller does not use vector table to prioritze interrupts
  IVT1WAY = ON,       // IVTLOCKED bit can be cleared and set only once
  LPBOREN = OFF,      // Low-Power BOR disabled
  BOREN = ON,         // SBOREN
  BORV = VBOR_1P9,    // Brown-out Reset Voltage (VBOR) set to 1.9V
  ZCD = OFF,          // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
  PPS1WAY = OFF,      // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
  STVREN = ON,        // Stack full/underflow will cause Reset
  LVP = ON,           // HV on MCLR/VPP must be used for programming
  XINST = OFF,        // Extended Instruction Set and Indexed Addressing Mode disabled
  WDTCPS = WDTCPS_31, // Divider ratio 1:65536; software control of WDTPS
  WDTE = OFF,         // WDT Disabled; SWDTEN is ignored
  WDTCWS = WDTCWS_7,  // window always open (100%); software control; keyed access not required
  WDTCCS = SC,        // Software Control
  BBSIZE = BBSIZE_512,// Boot Block size is 512 words
  BBEN = OFF,         // Boot block disabled
  SAFEN = OFF,        // SAF disabled
  DEBUG = OFF         // Background Debugger disabled
  WRTB = OFF,         // Boot Block not Write protected
  WRTC = OFF,         // Configuration registers not Write protected
  WRTD = OFF,         // Data EEPROM not Write protected
  WRTSAF = OFF,       // SAF not Write Protected
  WRTAPP = OFF,       // Application Block not write protected
  BOOTPINSEL = RC5,   // CRC on boot output pin is RC5
  BPEN = OFF,         // CRC on boot output pin disabled
  ODCON = OFF,        // Pin drives both high-going and low-going signals
  CP = OFF            // PFM and Data EEPROM code protection disabled
}
 ' this is what you sent with two changes
Config FEXTOSC = ECH            // EC (external clock) above 8 MHz
'config RSTOSC = EXTOSC          // EXTOSC operating per FEXTOSC bits (device manufacturing default)
Config RSTOSC = HFINTOSC_64MHZ // HFINTOSC with HFFRQ = 64 MHz and CDIV = 4:1
Config CLKOUTEN = OFF           // CLKOUT function is disabled
Config PR1WAY = ON              // PRLOCKED bit can be cleared and set only once
Config CSWEN = ON               // Writing to NOSC and NDIV is allowed
Config JTAGEN = OFF             // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
Config FCMEN = ON               // Fail-Safe Clock Monitor enabled
Config FCMENP = ON              // FSCM timer will set FSCMP bit and OSFIF interrupt on Primary XTAL failure
Config FCMENS = ON              // FSCM timer will set FSCMS bit and OSFIF interrupt on Secondary XTAL failure
Config MCLRE = EXTMCLR          // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
Config PWRTS = PWRT_64          // PWRT set at 64ms
Config MVECEN = OFF             // Interrupt contoller does not use vector table to prioritze interrupts
Config IVT1WAY = ON             // IVTLOCKED bit can be cleared and set only once
Config LPBOREN = OFF            // Low-Power BOR disabled
Config BOREN = ON               // Brown-out Reset enabled according to SBOREN
Config BORV = VBOR_1P9          // Brown-out Reset Voltage (VBOR) set to 1.9V
Config ZCD = OFF                // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
'config PPS1WAY = ON             // PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
Config PPS1WAY = OFF            // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Config STVREN = ON              // Stack full/underflow will cause Reset
Config LVP = ON                 // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
Config XINST = OFF              // Extended Instruction Set and Indexed Addressing Mode disabled
Config WDTCPS = WDTCPS_31       // Divider ratio 1:65536; software control of WDTPS
Config WDTE = OFF               // WDT Disabled; SWDTEN is ignored
Config WDTCWS = WDTCWS_7        // window always open (100%); software control; keyed access not required
Config WDTCCS = SC              // Software Control
Config BBSIZE = BBSIZE_512      // Boot Block size is 512 words
Config BBEN = OFF               // Boot block disabled
Config SAFEN = OFF              // SAF disabled
Config DEBUG = OFF              // Background Debugger disabled
Config WRTB = OFF               // Boot Block not Write protected
Config WRTC = OFF               // Configuration registers not Write protected
Config WRTD = OFF               // Data EEPROM not Write protected
Config WRTSAF = OFF             // SAF not Write Protected
Config WRTAPP = OFF             // Application Block not write protected
Config BOOTPINSEL = RC5         // CRC on boot output pin is RC5
Config BPEN = OFF               // CRC on boot output pin disabled
Config ODCON = OFF              // Pin drives both high-going and low-going signals
Config CP = OFF                 // PFM and Data EEPROM code protection disabled
    
// extended CONFIG data (XCONFIG)  - I did not look at these yet but have faith
#variable CRC_CONFIG = BOOTSCEN And BOOTPOR
#variable BCRCPOLT  = $AB
#variable BCRCPOLU  = $CD
#variable BCRCPOLH  = $EF
#variable BCRCPOLL  = $55

#variable BCRCSEEDT = $01
#variable BCRCSEEDU = $02
#variable BCRCSEEDH = $03
#variable BCRCSEEDL = $04
#variable BCRCEREST = $05
#variable BCRCERESU = $06
#variable BCRCERESH = $07
#variable BCRCERESL = $08
#variable CRCPOLT   = $09
#variable CRCPOLU   = $0a
#variable CRCPOLH   = $0b
#variable CRCPOLL   = $0c
#variable CRCSEEDT  = $0d
#variable CRCSEEDU  = $0e
#variable CRCSEEDH  = $0f
#variable CRCSEEDL  = $10
#variable CRCEREST  = $11
#variable CRCERESU  = $12
#variable CRCERESH  = $13
#variable CRCERESL  = $AA

' My code
#option USART_RX       = PORTC.7
#option USART_TX       = PORTC.6
#option USART3_TX      = PORTA.5 
#option USART3_RX      = PORTA.7

#option LCD_DATA       = PORTB.0
#option LCD_RS         = PORTB.4
#option LCD_EN         = PORTB.5
#option LCD_INIT_DELAY = 100
#option LCD_DATA_US    = 50
#option LCD_COMMAND_US = 2000

// import modules...
Include "USART.bas"
Include "USART3.bas"
Include "convert.bas"
Include "system.bas"
Include "PPS.bas"
Include "setdigitalio.bas"
Include "utils.bas"
Include "LCD.bas"
Include "EEPROM.bas"
Include "E32_DISPLAY.bas"
Include "string.bas"
Include "CONFIG_DISPLAY.bas"
Include "isrtimer.bas"
Include "config_Q84.bas"

I opened the 18F27Q84 file and found:

Code: Select all

// configuration fuses...
Public Config
   FEXTOSC(FEXTOSC) = [LP, XT, HS, OFF, ECL, ECM, ECH],
   RSTOSC(RSTOSC) = [HFINTOSC_64MHZ, RESERVED_1, EXTOSC_4PLL, RESERVED_2, SOSC, LFINTOSC, HFINTOSC_1MHZ, EXTOSC],
   CLKOUTEN(CLKOUTEN) = [ON, OFF],
   PR1WAY(PR1WAY) = [OFF, ON],
   CSWEN(CSWEN) = [OFF, ON],
   JTAGEN(JTAGEN) = [OFF, ON],
   FCMEN(FCMEN) = [OFF, ON],
   FCMENP(FCMENP) = [OFF, ON],
   FCMENS(FCMENS) = [OFF, ON],
   MCLRE(MCLRE) = [INTMCLR, EXTMCLR],
   PWRTS(PWRTS) = [PWRT_1, PWRT_16, PWRT_64, PWRT_OFF],
   MVECEN(MVECEN) = [OFF, ON],
   IVT1WAY(IVT1WAY) = [OFF, ON],
   LPBOREN(LPBOREN) = [ON, OFF],
   BOREN(BOREN) = [OFF, ON, NOSLP, SBORDIS],
   BORV(BORV) = [VBOR_2P85, VBOR_2P7, VBOR_2P45, VBOR_1P9],
   ZCD(ZCD) = [ON, OFF],
   PPS1WAY(PPS1WAY) = [OFF, ON],
   STVREN(STVREN) = [OFF, ON],
   LVP(LVP) = [OFF, ON],
   XINST(XINST) = [ON, OFF],
   WDTCPS(WDTCPS) = [WDTCPS_0, WDTCPS_1, WDTCPS_2, WDTCPS_3, WDTCPS_4, WDTCPS_5, WDTCPS_6, WDTCPS_7, WDTCPS_8, WDTCPS_9, WDTCPS_10, WDTCPS_11, WDTCPS_12, WDTCPS_13, WDTCPS_14, WDTCPS_15, WDTCPS_16, WDTCPS_17, WDTCPS_18, WDTCPS_19, WDTCPS_20, WDTCPS_21, WDTCPS_22, WDTCPS_23, WDTCPS_24, WDTCPS_25, WDTCPS_26, WDTCPS_27, WDTCPS_28, WDTCPS_29, WDTCPS_30, WDTCPS_31],
   WDTE(WDTE) = [OFF, SWDTEN, NSLEEP, ON],
   WDTCWS(WDTCWS) = [WDTCWS_0, WDTCWS_1, WDTCWS_2, WDTCWS_3, WDTCWS_4, WDTCWS_5, WDTCWS_6, WDTCWS_7],
   WDTCCS(WDTCCS) = [LFINTOSC, MFINTOSC, SOSC, SC],
   BBSIZE(BBSIZE) = [BBSIZE_32768, BBSIZE_16384, BBSIZE_8192, BBSIZE_4096, BBSIZE_2048, BBSIZE_1024, BBSIZE_512],
   BBEN(BBEN) = [ON, OFF],
   SAFEN(SAFEN) = [ON, OFF],
   WRTB(WRTB) = [ON, OFF],
   WRTC(WRTC) = [ON, OFF],
   WRTD(WRTD) = [ON, OFF],
   WRTSAF(WRTSAF) = [ON, OFF],
   WRTAPP(WRTAPP) = [ON, OFF],
   BOOTPINSEL(BOOTPINSEL) = [RA4, RA2, RC4, RC5],
   BPEN(BPEN) = [ON, OFF],
   ODCON(ODCON) = [ON, OFF],
   CP(CP) = [ON, OFF]

There is not DEBUG. The data sheet does show DEBUG at CONFIG7.5. Is this a problem?

Thanks,
Garry

[Jerry Messina]

My mistake, Garry. I forgot I'm using an updated set of programs with some new features.
Remove the DEBUG for the time being.

Try something simple first just to verify the settings and programming, something like this should work if you have a pin/LED you can toggle...

Code: Select all

Device = 18F27Q84
Clock  = 64

Config
  FEXTOSC = OFF,      // Oscillator not enabled
  RSTOSC = HFINTOSC_64MHZ,// HFINTOSC with HFFRQ = 64 MHz and CDIV = 4:1
  CLKOUTEN = OFF,     // CLKOUT function is disabled
  PR1WAY = ON,        // PRLOCKED bit can be cleared and set only once
  CSWEN = OFF,        // The NOSC and NDIV bits cannot be changed by user software
  JTAGEN = OFF,       // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
  FCMEN = OFF,        // Fail-Safe Clock Monitor disabled
  FCMENP = ON,        // FSCM timer will not set FSCMP bit or OSFIF interrupt on Primary XTAL failure
  FCMENS = ON,        // FSCM timer will not set FSCMS bit or OSFIF interrupt on Secondary XTAL failure
  MCLRE = EXTMCLR,    // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR 
  PWRTS = PWRT_16,    // PWRT is 16 ms
  MVECEN = OFF,       // Interrupt contoller does not use vector table to prioritze interrupts
  IVT1WAY = ON,       // IVTLOCKED bit can be cleared and set only once
  LPBOREN = OFF,      // Low-Power BOR disabled
  BOREN = ON,         // SBOREN
  BORV = VBOR_1P9,    // Brown-out Reset Voltage (VBOR) set to 1.9V
  ZCD = OFF,          // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
  PPS1WAY = OFF,      // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
  STVREN = ON,        // Stack full/underflow will cause Reset
  LVP = ON,           // HV on MCLR/VPP must be used for programming
  XINST = OFF,        // Extended Instruction Set and Indexed Addressing Mode disabled
  WDTCPS = WDTCPS_31, // Divider ratio 1:65536; software control of WDTPS
  WDTE = OFF,         // WDT Disabled; SWDTEN is ignored
  WDTCWS = WDTCWS_7,  // window always open (100%); software control; keyed access not required
  WDTCCS = SC,        // Software Control
  BBSIZE = BBSIZE_512,// Boot Block size is 512 words
  BBEN = OFF,         // Boot block disabled
  SAFEN = OFF,        // SAF disabled
  WRTB = OFF,         // Boot Block not Write protected
  WRTC = OFF,         // Configuration registers not Write protected
  WRTD = OFF,         // Data EEPROM not Write protected
  WRTSAF = OFF,       // SAF not Write Protected
  WRTAPP = OFF,       // Application Block not write protected
  BOOTPINSEL = RC5,   // CRC on boot output pin is RC5
  BPEN = OFF,         // CRC on boot output pin disabled
  ODCON = OFF,        // Pin drives both high-going and low-going signals
  CP = OFF            // PFM and Data EEPROM code protection disabled

// try with this section commented out... these are the defaults so shouldn't be required
{ 
// extended CONFIG data (XCONFIG)
#variable CRC_CONFIG = $FF
#variable BCRCPOLT  = $FF
#variable BCRCPOLU  = $FF
#variable BCRCPOLH  = $FF
#variable BCRCPOLL  = $FF

#variable BCRCSEEDT = $FF
#variable BCRCSEEDU = $FF
#variable BCRCSEEDH = $FF
#variable BCRCSEEDL = $FF
#variable BCRCEREST = $FF
#variable BCRCERESU = $FF
#variable BCRCERESH = $FF
#variable BCRCERESL = $FF
#variable CRCPOLT   = $FF
#variable CRCPOLU   = $FF
#variable CRCPOLH   = $FF
#variable CRCPOLL   = $FF
#variable CRCSEEDT  = $FF
#variable CRCSEEDU  = $FF
#variable CRCSEEDH  = $FF
#variable CRCSEEDL  = $FF
#variable CRCEREST  = $FF
#variable CRCERESU  = $FF
#variable CRCERESH  = $FF
#variable CRCERESL  = $FF
Include "config_Q84.bas"
}

' My code
#option USART_RX       = PORTC.7
#option USART_TX       = PORTC.6
#option USART3_TX      = PORTA.5 
#option USART3_RX      = PORTA.7

#option LCD_DATA       = PORTB.0
#option LCD_RS         = PORTB.4
#option LCD_EN         = PORTB.5
#option LCD_INIT_DELAY = 100
#option LCD_DATA_US    = 50
#option LCD_COMMAND_US = 2000

// import modules...
include "intosc.bas"
#option DIGITALIO_INIT=true     // automatically call setalldigital at startup
include "setdigitalio.bas"
// other imports would go here

// start of main code
// do something simple... flash an led
dim LED_PIN as PORTB.0

low (LED_PIN)
while (true)
	toggle(LED_PIN)
	delayms(500)
end while

[garryp4]

Jerry: That took care of it

Thanks you very much!

[Jerry Messina]

Great. Glad you're up and running.

If you notice anything funny as you add your real code, just yell.
There's a lot that's changed with these new chips so the libs may need some massaging.