Thanks for the info. I have included my code with what I had from the ConfigGenerator commented out and what you sent with two changes. I get an error at the DEBUG line:
Code: Select all
Device = 18F27Q84
Clock = 64
{ This is what I had from the ConfigGenerator
Config
FEXTOSC = OFF, // Oscillator not enabled
RSTOSC = HFINTOSC_64MHZ,// HFINTOSC with HFFRQ = 64 MHz and CDIV = 4:1
CLKOUTEN = OFF, // CLKOUT function is disabled
PR1WAY = ON, // PRLOCKED bit can be cleared and set only once
CSWEN = OFF, // The NOSC and NDIV bits cannot be changed by user software
JTAGEN = OFF, // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
FCMEN = ON, // Fail-Safe Clock Monitor disabled
FCMENP = ON, // FSCM timer will not set FSCMP bit or OSFIF interrupt on Primary XTAL failure
FCMENS = ON, // FSCM timer will not set FSCMS bit or OSFIF interrupt on Secondary XTAL failure
MCLRE = EXTMCLR, // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
PWRTS = PWRT_16, // PWRT is 16 ms
MVECEN = OFF, // Interrupt contoller does not use vector table to prioritze interrupts
IVT1WAY = ON, // IVTLOCKED bit can be cleared and set only once
LPBOREN = OFF, // Low-Power BOR disabled
BOREN = ON, // SBOREN
BORV = VBOR_1P9, // Brown-out Reset Voltage (VBOR) set to 1.9V
ZCD = OFF, // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
PPS1WAY = OFF, // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
STVREN = ON, // Stack full/underflow will cause Reset
LVP = ON, // HV on MCLR/VPP must be used for programming
XINST = OFF, // Extended Instruction Set and Indexed Addressing Mode disabled
WDTCPS = WDTCPS_31, // Divider ratio 1:65536; software control of WDTPS
WDTE = OFF, // WDT Disabled; SWDTEN is ignored
WDTCWS = WDTCWS_7, // window always open (100%); software control; keyed access not required
WDTCCS = SC, // Software Control
BBSIZE = BBSIZE_512,// Boot Block size is 512 words
BBEN = OFF, // Boot block disabled
SAFEN = OFF, // SAF disabled
DEBUG = OFF // Background Debugger disabled
WRTB = OFF, // Boot Block not Write protected
WRTC = OFF, // Configuration registers not Write protected
WRTD = OFF, // Data EEPROM not Write protected
WRTSAF = OFF, // SAF not Write Protected
WRTAPP = OFF, // Application Block not write protected
BOOTPINSEL = RC5, // CRC on boot output pin is RC5
BPEN = OFF, // CRC on boot output pin disabled
ODCON = OFF, // Pin drives both high-going and low-going signals
CP = OFF // PFM and Data EEPROM code protection disabled
}
' this is what you sent with two changes
Config FEXTOSC = ECH // EC (external clock) above 8 MHz
'config RSTOSC = EXTOSC // EXTOSC operating per FEXTOSC bits (device manufacturing default)
Config RSTOSC = HFINTOSC_64MHZ // HFINTOSC with HFFRQ = 64 MHz and CDIV = 4:1
Config CLKOUTEN = OFF // CLKOUT function is disabled
Config PR1WAY = ON // PRLOCKED bit can be cleared and set only once
Config CSWEN = ON // Writing to NOSC and NDIV is allowed
Config JTAGEN = OFF // Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
Config FCMEN = ON // Fail-Safe Clock Monitor enabled
Config FCMENP = ON // FSCM timer will set FSCMP bit and OSFIF interrupt on Primary XTAL failure
Config FCMENS = ON // FSCM timer will set FSCMS bit and OSFIF interrupt on Secondary XTAL failure
Config MCLRE = EXTMCLR // If LVP = 0, MCLR pin is MCLR; If LVP = 1, RE3 pin function is MCLR
Config PWRTS = PWRT_64 // PWRT set at 64ms
Config MVECEN = OFF // Interrupt contoller does not use vector table to prioritze interrupts
Config IVT1WAY = ON // IVTLOCKED bit can be cleared and set only once
Config LPBOREN = OFF // Low-Power BOR disabled
Config BOREN = ON // Brown-out Reset enabled according to SBOREN
Config BORV = VBOR_1P9 // Brown-out Reset Voltage (VBOR) set to 1.9V
Config ZCD = OFF // ZCD module is disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
'config PPS1WAY = ON // PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
Config PPS1WAY = OFF // PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Config STVREN = ON // Stack full/underflow will cause Reset
Config LVP = ON // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored
Config XINST = OFF // Extended Instruction Set and Indexed Addressing Mode disabled
Config WDTCPS = WDTCPS_31 // Divider ratio 1:65536; software control of WDTPS
Config WDTE = OFF // WDT Disabled; SWDTEN is ignored
Config WDTCWS = WDTCWS_7 // window always open (100%); software control; keyed access not required
Config WDTCCS = SC // Software Control
Config BBSIZE = BBSIZE_512 // Boot Block size is 512 words
Config BBEN = OFF // Boot block disabled
Config SAFEN = OFF // SAF disabled
Config DEBUG = OFF // Background Debugger disabled
Config WRTB = OFF // Boot Block not Write protected
Config WRTC = OFF // Configuration registers not Write protected
Config WRTD = OFF // Data EEPROM not Write protected
Config WRTSAF = OFF // SAF not Write Protected
Config WRTAPP = OFF // Application Block not write protected
Config BOOTPINSEL = RC5 // CRC on boot output pin is RC5
Config BPEN = OFF // CRC on boot output pin disabled
Config ODCON = OFF // Pin drives both high-going and low-going signals
Config CP = OFF // PFM and Data EEPROM code protection disabled
// extended CONFIG data (XCONFIG) - I did not look at these yet but have faith
#variable CRC_CONFIG = BOOTSCEN And BOOTPOR
#variable BCRCPOLT = $AB
#variable BCRCPOLU = $CD
#variable BCRCPOLH = $EF
#variable BCRCPOLL = $55
#variable BCRCSEEDT = $01
#variable BCRCSEEDU = $02
#variable BCRCSEEDH = $03
#variable BCRCSEEDL = $04
#variable BCRCEREST = $05
#variable BCRCERESU = $06
#variable BCRCERESH = $07
#variable BCRCERESL = $08
#variable CRCPOLT = $09
#variable CRCPOLU = $0a
#variable CRCPOLH = $0b
#variable CRCPOLL = $0c
#variable CRCSEEDT = $0d
#variable CRCSEEDU = $0e
#variable CRCSEEDH = $0f
#variable CRCSEEDL = $10
#variable CRCEREST = $11
#variable CRCERESU = $12
#variable CRCERESH = $13
#variable CRCERESL = $AA
' My code
#option USART_RX = PORTC.7
#option USART_TX = PORTC.6
#option USART3_TX = PORTA.5
#option USART3_RX = PORTA.7
#option LCD_DATA = PORTB.0
#option LCD_RS = PORTB.4
#option LCD_EN = PORTB.5
#option LCD_INIT_DELAY = 100
#option LCD_DATA_US = 50
#option LCD_COMMAND_US = 2000
// import modules...
Include "USART.bas"
Include "USART3.bas"
Include "convert.bas"
Include "system.bas"
Include "PPS.bas"
Include "setdigitalio.bas"
Include "utils.bas"
Include "LCD.bas"
Include "EEPROM.bas"
Include "E32_DISPLAY.bas"
Include "string.bas"
Include "CONFIG_DISPLAY.bas"
Include "isrtimer.bas"
Include "config_Q84.bas"
Code: Select all
// configuration fuses...
Public Config
FEXTOSC(FEXTOSC) = [LP, XT, HS, OFF, ECL, ECM, ECH],
RSTOSC(RSTOSC) = [HFINTOSC_64MHZ, RESERVED_1, EXTOSC_4PLL, RESERVED_2, SOSC, LFINTOSC, HFINTOSC_1MHZ, EXTOSC],
CLKOUTEN(CLKOUTEN) = [ON, OFF],
PR1WAY(PR1WAY) = [OFF, ON],
CSWEN(CSWEN) = [OFF, ON],
JTAGEN(JTAGEN) = [OFF, ON],
FCMEN(FCMEN) = [OFF, ON],
FCMENP(FCMENP) = [OFF, ON],
FCMENS(FCMENS) = [OFF, ON],
MCLRE(MCLRE) = [INTMCLR, EXTMCLR],
PWRTS(PWRTS) = [PWRT_1, PWRT_16, PWRT_64, PWRT_OFF],
MVECEN(MVECEN) = [OFF, ON],
IVT1WAY(IVT1WAY) = [OFF, ON],
LPBOREN(LPBOREN) = [ON, OFF],
BOREN(BOREN) = [OFF, ON, NOSLP, SBORDIS],
BORV(BORV) = [VBOR_2P85, VBOR_2P7, VBOR_2P45, VBOR_1P9],
ZCD(ZCD) = [ON, OFF],
PPS1WAY(PPS1WAY) = [OFF, ON],
STVREN(STVREN) = [OFF, ON],
LVP(LVP) = [OFF, ON],
XINST(XINST) = [ON, OFF],
WDTCPS(WDTCPS) = [WDTCPS_0, WDTCPS_1, WDTCPS_2, WDTCPS_3, WDTCPS_4, WDTCPS_5, WDTCPS_6, WDTCPS_7, WDTCPS_8, WDTCPS_9, WDTCPS_10, WDTCPS_11, WDTCPS_12, WDTCPS_13, WDTCPS_14, WDTCPS_15, WDTCPS_16, WDTCPS_17, WDTCPS_18, WDTCPS_19, WDTCPS_20, WDTCPS_21, WDTCPS_22, WDTCPS_23, WDTCPS_24, WDTCPS_25, WDTCPS_26, WDTCPS_27, WDTCPS_28, WDTCPS_29, WDTCPS_30, WDTCPS_31],
WDTE(WDTE) = [OFF, SWDTEN, NSLEEP, ON],
WDTCWS(WDTCWS) = [WDTCWS_0, WDTCWS_1, WDTCWS_2, WDTCWS_3, WDTCWS_4, WDTCWS_5, WDTCWS_6, WDTCWS_7],
WDTCCS(WDTCCS) = [LFINTOSC, MFINTOSC, SOSC, SC],
BBSIZE(BBSIZE) = [BBSIZE_32768, BBSIZE_16384, BBSIZE_8192, BBSIZE_4096, BBSIZE_2048, BBSIZE_1024, BBSIZE_512],
BBEN(BBEN) = [ON, OFF],
SAFEN(SAFEN) = [ON, OFF],
WRTB(WRTB) = [ON, OFF],
WRTC(WRTC) = [ON, OFF],
WRTD(WRTD) = [ON, OFF],
WRTSAF(WRTSAF) = [ON, OFF],
WRTAPP(WRTAPP) = [ON, OFF],
BOOTPINSEL(BOOTPINSEL) = [RA4, RA2, RC4, RC5],
BPEN(BPEN) = [ON, OFF],
ODCON(ODCON) = [ON, OFF],
CP(CP) = [ON, OFF]
There is not DEBUG. The data sheet does show DEBUG at CONFIG7.5. Is this a problem?