There's a nasty silicon errata just published that basically makes the chips unusable!
18FxxQ43 errata issue 1.4.1
silicon rev B0
SRAM Readback
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Following a device power up sequence, there is a possibility that some SRAM locations will not return the expected
written value but will read back '00' instead.
Work around:
None. The device can only recover by power cycling.
This erroneous condition can be detected by running the following code that writes non-zero values to SRAM and
then verifies the returned read values are not '00'. If a returned value is '00', the application code should be put
into a safe state until a POR event occurs. This code should be executed immediately after power-up.
If the test passes, device operation will be normal.
Code: Select all
// SRAM test
// For devices up to 2K RAM
FSR0 = $0cff // Write data into RAM
INDF0 = $55
PROD = INDF0 // Read back data
if (PROD = 0) then
SAFE_STATE() // RAM incorrectly read, suspend operation and go to safe state
endif
// For devices with more than 2K of SRAM add the following code
FSR0 = $14ff // Write data into RAM
INDF0 = $55
PROD = INDF0 // Read back data
if (PROD = 0) then
SAFE_STATE() // RAM incorrectly read, suspend operation and go to safe state
endif
// For devices with more than 4K of SRAM add the following code
FSR0 = $24ff // Write data into RAM
INDF0 = $55
PROD = INDF0 // Read back data
if (PROD = 0) then
SAFE_STATE() // RAM incorrectly read, suspend operation and go to safe state
endif